This invention relates, in general, to fabricating isolated regions on a semiconductor wafer, and more particularly, to a method of fabricating a dielectric isolated area.
Dielectric isolated circuits (DIC) are comprised of isolated, monosilicon islands electrically isolated from each other and from a supporting substrate by a dielectric material. The dielectric material, generally silicon dioxide or silicon nitride, provides excellent electrical isolation which reduces parasitic capacitances that adversely affect circuit performance. Dielectric isolation provides for better isolation than other conventional isolation techniques.
Traditional dielectric isolated circuits have been fabricated by etching a moat in a silicon substrate, and subsequently oxidizing and refilling the moat with a thick, high resistivity polysilicon layer, which is used as a handle wafer. The non-deposited side of the silicon substrate is then ground and polished back to the bottom of the etched moat for formation of the isolated silicon islands. Deposition of the thick polysilicon layer on one side of the substrate causes severe wafer warpage, which is disadvantageous for integrated circuit manufacturing. Another disadvantage of this process is its high cost of manufacturing, because of its complexity and resultant low yield. Although dielectric isolated structures provide the ideal structure for monolithic microwave integrated circuits, usage of dielectric isolated circuit processing has been limited due to its disadvantages.
Accordingly, it would be desirable to provide an improved method of fabricating dielectric isolated areas on semiconductor wafers.